1. Field of the Invention
The invention pertains to the field of integrated circuits. More particularly, the invention pertains to programmable logic integrated circuit devices.
2. Description of Related Art
Programmable logic integrated circuit devices (PLDs) are known in the art. A PLD comprises a programmable logic block with any number of initially uncommitted logic modules arranged in a programmable logic array along with an appropriate amount of initially uncommitted routing resources. Logic modules are circuits which can be configured to perform a variety of logic functions like, for example, AND-gates, OR-gates, NAND-gates, NOR-gates, XOR-gates, XNOR-gates, inverters, multiplexers, adders, latches, and flip/flops. Routing resources can include a mix of components such as, for example, wires, switches, multiplexers, and buffers. Logic modules, routing resources, and other features like, for example, I/O buffers and memory blocks, are the programmable elements of the PLD.
The programmable elements have associated control elements (sometimes known as programming bits or configuration bits) which determine their functionality. The control elements may be thought of as binary bits having values such as on/off, conductive/non-conductive, true/false, or logic-1/logic-0 depending on the context. The control elements vary according to the technology employed and their mode of data storage may be either volatile or non-volatile. Volatile control elements, such as SRAM bits, lose their programming data when the PLD power supply is disconnected, disabled or turned off. Non-volatile control elements, such as antifuses and floating gate transistors, do not lose their programming data when the PLD power supply is removed. Some control elements, such as antifuses, can be programmed only one time and cannot be erased. Other control elements, such as SRAM bits and floating gate transistors, can have their programming data erased and may be reprogrammed many times. The detailed circuit implementation of the logic modules and routing resources can vary greatly and must be appropriate for the type of control element used.
Like most integrated circuits, PLDs typically have an input/output (I/O) ring surrounding a central core, though other approaches are possible. The I/O ring contains the input and output buffers that interface to circuits external to the PLD as well as the power supply and ground connections. Some of the input and output buffers are typically dedicated to control functions. Others are programmable elements which can be part of an end user's logic design. It is common for the programmable element inputs and outputs (also called user inputs or user input buffers and user outputs or user output buffers) to pair equal numbers of input buffers and output buffers together to form input/output buffers (also called I/O buffers or user I/O buffers or user I/Os or sometimes simply I/Os). In some PLDs, one or more of the inputs, outputs, or I/Os can be shared between user logic design functions and control functions.
In a pure PLD, the central core contains a programmable logic block comprising the majority of the programmable elements and control elements. The programmable logic block also typically contains a variety of control circuits. There may be other control circuits present either inside the central core or inside the I/O ring or divided between the central core and the I/O ring. This control circuitry handles various tasks such as testing the PLD functionality, programming the control elements, or transitioning the PLD from one mode of operation to another. In a hybrid PLD, there are typically other function blocks available to the user during normal operation such as central processing units, analog blocks, custom logic blocks, and large volatile or non-volatile memory blocks. In some cases, the programmable logic block may be a minority of the total central core circuitry.
An end user's logic design is typically implemented by use of a computer program product (also known as software or, more specifically, design software) produced by the PLD manufacturer and distributed by means of a computer-readable medium such as providing a CD-ROM to the end user or making the design software downloadable over the internet. Typically the manufacturer supplies a library of design elements (also known as library elements) as part of the computer program product. The library design elements provide a layer of insulation between the end user and the circuit details of the programmable elements, control elements, and the other PLD features available to the end user. This makes the design software easier to use for the end user and simplifies the manufacturer's task of processing the end user's logic design by the various tools in the design software.
Once the end user's logic design is complete, the design software produces the data structure necessary to program the PLD. This typically results in a data structure containing a binary bit for each control element in the PLD (also known as programming data or bit stream data) in a computer readable medium appropriate for use in the end user's system. For SRAM-based PLDs this is typically a PROM (or EPROM or EEPROM or flash PROM) mounted on the printed circuit board next to the PLD. For antifuse-based and most floating gate transistor-based PLDs, this is typically a file stored on a hard disk, CD-ROM, or similar device. This file can then be transferred to a programming system where the PLD is programmed prior to installation in the end user's system. Alternatively, the file can be used for In System Programming (ISP) after the PLD is installed.
In the PLDs of the prior art, there are control circuits present on the integrated circuit device which assist the programming process. For example, in the AX antifuse-based field programmable gate array (FPGA) family offered by Actel Corporation of Mountain View, Calif., there is a JTAG compatible test port which allows an external programmer to manipulate state-machine based logic to transfer a serial bit stream of programming data from the external programmer to the internal control elements. (FPGAs are a type of PLD.)
Another example is Actel's ProASIC3 flash-based family FPGA. While the internal circuitry is very different from the AX family due to the different programming technology, this family also has a JTAG port coupled to state machine-based logic which an external programmer uses to transfer the programming data to the configurable elements.
Typically while a PLD is being programmed, the device is placed in a special programming mode where normal operation of the logic design in the programmable logic array in the programmable logic block is disabled. Once programmed, the control logic allows the PLD to be operated normally according to the end user's logic design.
A significant limitation of the control circuits of the prior art is their lack of flexibility. A JTAG port can only execute the instructions its designer hardwires into it. Similarly, a state machine can only perform the tasks dictated by its state diagram and transition table. Even a very sophisticated state machine-based control system like the one in the ProASIC3 family which has a non-volatile flash memory on board which is used to parameterize its functionality is restricted to the operations dictated by its hard-wired structure and cannot be used in a manner not anticipated by its designer.
There are several reasons why this can be significant. First, a PLD with prior art control logic may not work properly the first time a new product is manufactured. Identifying the problem can be a long and arduous task, and if the debug process requires the control logic to do something outside its design and parameter limits, it can be difficult or impossible to make a correct diagnosis. Second, the proper operation of a PLD depends greatly on the semiconductor process in which it is manufactured. If some change in the process occurs that requires a new or different programming technique that is outside the capabilities of the control logic, it must be redesigned to implement the new functionality. Third, there are many tasks on complicated, high-end PLDs, such as testing certain portions of the PLD not easily accessible by means of programming or external pins that are implemented by extending the functionality of the control logic to cover those operations. This can make the design of the control logic even more complicated and potentially error prone.
Employing CPUs on PLDs for microcontroller applications is known in the art. For example, Xilinx, Inc., of San Jose, Calif. offers hardware Power PC 405 RISC processor cores in its Virtex-2 PRO line of FPGAs. Several FPGA manufactures offer soft processor cores that can be built out of logic modules and routing resources like, for example, the Nios processor core offered by Altera Corporation of San Jose, Calif., and the ARM7 processor core offered by Actel. However, none of these prior art processors can be used for programming the PLD or performing other PLD internal control functions and can only be accessed as part of an end user's logic design. By using a microcontroller to replace the control logic, all of the limitations of the prior art discussed above can be overcome since the control function becomes a computer program product in a computer readable medium (software, or more particularly known as firmware in microcontroller applications) which can be changed with relative ease if the need arises—particularly in a non-volatile technology where the new software can be stored and remain on-chip by means of programming control elements. Furthermore, by utilizing the microcontroller to perform other tasks, and not just for programming and test functions, additional functionality can be offered to the end user that is completely unavailable in prior art PLDs.